Dr. V. Rajmohan M.E.,Ph.D - Saveetha (Autonomous) Engineering College

rajmohan Professor

Academic Scores:
ELECTRONIC CIRCUITS II                     224.0044
Signals and Systems                               198.5685
Signals and Systems                               176.6145
SIGNALS AND SYSTEMS                        203.5512
VLSI Design                                             150.0403
VLSI Design                                             167.4311

Education:

Ph.D	Low Power VLSI System	Anna University
M.E	VLSI System	National Institute of Technology, Trichy
B.E	Electronics And Communication Engineering	Thiagarajar College of Engineering, Madurai

Other Details:

Area of Specialization:

VLSI System

Research Interests:

Low Power VLSI System
Reversible Circuit Design
Memristive Devices

Selected Publications:

Journal Publications:

Rajmohan, V. and Uma Maheswari, O., 2016, ‘Design of Compact Baugh-Wooley Multiplier Using Reversible Logic’, Circuits and Systems, Vol.7, pp. 1522-1529. doi:10.4236/cs.2016.78133.
V. Rajmohan, Dr. O. Uma Maheswari, ‘Improved Baugh-Wooley Multiplier using Cadence Register Transfer Level Logic for Power Consumption’, Journal of Computational and Theoretical Nano science, Vol. 14, no. 1, pp. 277-283, 2017. doi: 10.1166/jctn.2016.6317.
“Scalable Modular Design of finite field Multipliers Using Systolic Architectures” published in International Journal of VLSI Design, Vol (2), Issue 1, June 2011 pp: 13 – 18.
“A REVERSIBLE DESIGN OF BCD MULTIPLIER” published in Journal of Computing, Vol (2), Issue 11, Nov 2010 pp.112-117.
“A Novel Reversible Design of Unified Single Digit BCD Adder-Subtractor” published in International Journal of Computer Theory and Engineering, Vol (3), Issue 5, Oct 2011 pp: 702 – 705.
“Optimized Shift Register Design Using Reversible Logic” at International Conference on Electronics Computer Technology at Kanyakumari, India during 8-10, April 2011.
“Design of Counters Using Reversible Logic” at International Conference on Networks and Computer Science at Kanyakumari, India during 8-10, April 2011.
“FPGA Implementation of Viterbi Algorithm for Processing of Forward Error Control in Software Radio Receiver” at International Conference on Communication and Signal Processing at Karunya University, Coimbatore during 17-18, March 2011.
“Scalable Modular Design of Finite Field Multipliers Using Systolic Architecture” at International Conference on Communication and Signal Processing at Karunya University, Coimbatore during 17-18, March 2011.
“Optimization of Reversible BCD Adder in terms of Number of Lines” at International Conference on Information Communication & Embedded System at SA Engineering College, Chennai during 23-24, February 2011.
“ Low Power Implementation of Survivor Path Processing in ML Decoding Algorithm Using RE, TB and TF Methods in FPGA” at International Conference on Smart Technologies for Materials, Communication, Controls, Computing and Energy at Vel-Tech High-Tech University, Chennai during 5-7, January 2011.
“A Low Power Architecture of Viterbi Decoder for Processing of Forward Error Control in Software Radio Receiver” at International Conference on Smart Technologies for Materials, Communication, Controls, Computing and Energy at Vel-Tech High-Tech University, Chennai during 5-7, January 2011.
“Designing of High Speed Multiplier” at the National Conference on Microwave and Optical Communication at Alagappa Chettiar College of Engineering and Technology, Karaikudi, Tamilnadu on March 30, 2011.
“Development of Variable Length FFT Processor” at the 2nd National Conference on Recent Advances in Electronics & Communicatin Technologies at Guru Nanak Dev Engineering College, Ludhiana during March 04-05, 2011.
“ Dynamically Reconfigurable Solution in the digital Baseband processing for Future Radio Devices” at the National Conference on Innovative Technologies in Electrical and Electronics Systems at Muthayammal Engineering College, Rasipuram on Feb, 24-25 ’10.
“An analysis on Digital Image Steganography method against histrogram” at the National Conference on Communication, Computation, Control and Automation at Sri Ramakrishna Institute of Technology, Coimbatore on April 23 – 24 ’10.
A paper on Reversible Multiplier
A paper on Low Power Booth Encoder and Decoder
Preparing the manuscripts
Question paper setter – PG Programme – Sathyabama University
Integration, the VLSI Journal – Reviewer
IEEE Transactions on Very Large Scale Integration Systems – Reviewer
- Organized ICMR sponsored two days’ workshop on Internet of Every Thing for the Next Generation Ubiquitous Healthcare Services during 13 – 14th October, 2017 at Sri Sakthi Institute of Engineering and Technology, Coimbatore.
- Organized 10 days’ workshop on ‘Analog Electronics’ at Loyola-ICAM College of Engineering and Technology, Chennai conducted by IIT Kharagpur during June 2013.
- “IMAGE PROCESSING TECHNIQUES” at Hotel Chennai Delux conducted by IET Chennai Network on 23rd March, 2010.
- Hands on training on “ANALOG MIXED SIGNAL – DIGITAL DESIGN USING CADENCE TOOLS” at ICT Academy of Tamilnadu, Perungudi, Chennai conducted by Cadence India during20th – 22nd August 2010.

International Conference:

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Working Papers:

Work in Progress:

Academic Experience:

Professor in ECE Dept, Saveetha Engineering College from Dec. 2017.
Associate Professos in ECE Dept., Sri Sakthi Institute of Engineering and Technology, Coimbatore from May 2017
Assistant Professor in ECE Dept., Loyola – ICAM College of Engineering and Technology, Chennai from July 2011.
Assistant Professor in ECE Dept., Hindustan Institute of Technology and Science, Chennai from Jan 2008.
Assistant Professor in ECE Dept., Dr. MGR Educational & Research Institute, Chennai from July 2006.
Lecturer in ECE Dept., RVS College of Engineering and Technology, Dindigul from July 2003.
Lecturer in ECE Dept., Odaiyappah College of Engineering and Technology, Theni from Feb 2001.

Guideship Details

Professional Development Activities:

Conferences/Seminars/Workshops Attended